Blar i NTNU Open på forfatter "Austbø, Knut"

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    • Clock Tree Power Analysis 

      Austbø, Knut (Master thesis, 2016)
      The buffered clock tree structure is commonly used to distribute the clock signal to the memory elements in digital circuits. Since the clock signal is used as a temporal reference, it has to be distributed to the registers ...

    • RTL Power Estimation Flow and Its Use in Power Optimization 

      Nesset, Sondre Rennan (Master thesis, 2018)
      The increased complexity and low-power requirements of integrated circuit design demands reliable and accurate power estimations in the RTL phase, for effective design tradeoffs early in the design phase. This thesis ...